The invention relates to a semiconductor memory, comprising a memory matrix of rows and columns of memory cells for storing, per row, data information and also error protective redundant information, said memory comprising an on-chip error correction device which is fed by column outputs of the memory matrix, for receiving one symbol for each accessed column, and first column selection means which are fed by said error correction device in order to present output signals for further use.
A semiconductor memory of this kind is described in U.S. Pat. No. 4,604,749. The known memory is a read-only memory (ROM). In addition to the first column selection means, the memory also comprises second column selection means which are connected between the memory matrix and the correction device. These second column selection means select a comparatively small number of columns, so that a comparatively short code word is presented to the error correction device. It will be apparent that the terms "columns" and "rows" can be interchanged throughout in the reference. The described code is a so-called shortened (38, 32, 3) Hamming code with 38 code bits, 32 data bits and a minimum distance of 3 over the bits. As a result, a single-bit error can be corrected in 32 data bits, using a redundancy of 6/32=19%. The first column selection means select each time a single byte (8 bits) from the 32-bit word, which byte appears on an output. The efficiency of this code is comparatively low. Improvement of the efficiency would necessitate a longer code word, however, the implementation is already complex for an 38-bit code word. On the one hand this requires a comparatively large surface area on the integrated circuit and on the other hand the time required for decoding is comparatively long, so that the memory will be slower. Finally, the described organization is not suitable for a random access memory (RAM).